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TargetOS Kernel Benchmark


Semaphore Test

MPC5200

ARM9

MCF5474

MCF5282

NIOS2

semPend() with waiting token

0.2 usec

1.2 usec

0.5 usec

4.0 usec

2.9 usec

semPost() with no task waiting

0.1 usec

0.9 usec

0.5 usec

5.0 usec

4.4 usec

semPost() with task made ready, no context switch

1.1 usec

4.6 usec

2.5 usec

17.0 usec

12.3 usec

semPost() with context switch

0.8 usec

3.7 usec

2.5 usec

21.0 usec

9.2 usec

semPend() with context switch

0.8 usec

4.1 usec

2.6 usec

20.0 usec

15.2 usec


Queue Test

MPC5200

ARM9

MCF5474

MCF5282

NIOS2

quePend() with waiting message

1.0 usec

3.1 usec

1.2 usec

10.0 usec

9.7 usec

quePost() with no task waiting

0.8 usec

3.3 usec

1.7 usec

13.0 usec

15.3 usec

quePost() with task made ready, no context switch

1.0 usec

3.6 usec

2.0 usec

19.0 usec

12.9 usec

quePost() with context switch

0.5 usec

4.5 usec

3.7 usec

22.0 usec

13.8 usec

quePend() with context switch

0.8 usec

4.5 usec

2.6 usec

21.0 usec

20.2 usec


Nexus Test

MPC5200

ARM9

MCF5474

MCF5282

NIOS2

nexPost() with no task waiting

0.5 usec

1.8 usec

1.0 usec

5.0 usec

3.8 usec

nexPost() with 1 task made ready, no context switch

2.6 usec

7.4 usec

3.1 usec

22.0 usec

17.6 usec

nexPost() with 2 tasks readied, no context switch

2.6 usec

7.0 usec

3.7 usec

33.0 usec

13.6 usec

nexPost() from ISR with >1 task waiting

1.3 usec

4.5 usec

3.7 usec

22.0 usec

13.8 usec

nexPost() with context switch

2.9 usec

8.5 usec

4.5 usec

35.0 usec

17.9 usec

nexPend() with context switch

1.0 usec

4.3 usec

2.5 usec

20.0 usec

14.7 usec


The results are for the following configurations:

board:      phyCORE-MPC5200B-I/O - MPC200B at 396 MHz
compiler: GCC v4.3.2
CPU:        Instruction cache enabled, data cache enabled in copy-back mode

board:      JRM X920T - ARM9 at 60 MHz
compiler: GCC v4.3.2
CPU:       Instruction cache enabled, data cache enabled in copy-back mode

board:      M5474LITE - MCF5474 at 132 MHz
compiler: GCC v4.3.2
CPU:       Instruction cache enabled, data cache enabled in write-through mode

board:      M5282LITE - MCF5282 at 64 MHz
compiler: GCC v4.3.2
CPU:       Instruction cache enabled, buffered writes enabled

board:     
NEEK NIOS2/fast at 100 MHz
compiler: GCC v4.1.2
CPU:       4KB instruction cache, 4KB copy-back data cache

For more information on kernel benchmark, please contact us:

Blunk Microsystems
8880 Cal Center Drive, Suite 400
Sacramento, CA 95826
Tel: (408)323-1758
Fax: (408)323-1757
Email: sales@blunkmicro.com