XP920T Board Support Package for TargetOS, RTOS for ARM
Performs low level initialization of Atmel's AT91RM9200 microcontroller, including MMU, caches, interrupt controller, clock generator, SDRAM controller, etc. allowing TargetOS™ applications to boot from Flash.
Interrupt-driven and polled-mode UART driver for AT91RM9200's USART channels supports the stream I/O routines (printf(), scanf(), etc.) in the TargetOS Standard C library. Baud rate, parity, flow control mode, and number of stop bits are programmable.
Ethernet MAC (EMAC) driver uses the highest negotiable combination of half and full duplex, 10 and 100 Mbps, and implements a zero-copy interface to TargetTCP™, Blunk Microsystems' high performance TCP/IP stack. Supports TFTP downloads, FTP transfers, Telnet access to the TargetOS command line monitor, and other TCP/IP applications.
System Timer (ST) driver implements the kernel tick interrupt used for task sleeps and system call timeouts. The default tick interrupt frequency is 128 Hz.
Drivers for Timer Counters (TC) 1-3 allow either periodic or one-time calls to user-provided callback functions after programmable delays. The default resolution is 1 us and the maximum delay is 2 sec. Timer Counters 4 and 5 implement the TargetOS 32-bit system timer for profiling and short delays.
DS1746 time-of-day clock driver supports the TargetOS Standard C library time-related functions. The time-of-day and date can be set by application programs or by the TargetOS boot menu..
NOR StrataFlash driver supports TargetFFS® and the menu-driven TargetOS flash programmer for installing boot applications. The programmer supports ELF and S-record formats, accepting input from either a file, UART channel, FTP, or TFTP. TargetFFS has a POSIX and Standard C compliant file system API and provides guaranteed file system integrity across unexpected shutdowns.
Enables the AT91RM9200 MMU. Accesses to unsupported address ranges are caught and reported to the application as bus errors.
Enables AT91RM9200 data and instruction caches. The instruction cache is enabled for all accesses. Data accesses to the SDRAM use copy-back cache mode. All other data accesses are cache inhibited. Includes service calls to flush, invalidate, and synchronize the instruction and data caches.
Integrated with CrossStep™, Blunk Microsystem's IDE for embedded development with an integrated project builder, kernel-aware source code debugger, on-chip debug connections for board bring-up and Ethernet debug connections for fast application development.
Royalty free License. Includes full ANSI C source code, default compiler settings, linker command files, user's manual, and one year of technical support.